1. Field of the Invention
The present invention relates to an image processing apparatus.
2. Description of the Related Art
An image processing apparatus such as a digital camera generally performs image processing such as noise reduction, optical distortion correction, and image rotation. For example, there is known a technique of noise reduction processing, which writes, in a DRAM (Dynamic Random Access Memory), a plurality of types of image data generated by dividing image data into a plurality of frequency bands. After that, appropriate filter processing is performed for each image data read out from the DRAM, and the image data processed on a frequency band basis are frequency-composited again, thereby reducing noise.
In such image processing, a line memory such as an SRAM is considered to be used to speed up the filter processing. However, the ever-growing numbers of pixels included in recent images increase the necessary line memory capacity and make the circuit scale large. Additionally, performing such image processing at a higher speed becomes more important along with the recent increase in the number of still image frames in continuous shooting and improvement of moving image frame rates.
Regarding these problems, there are various conventionally known techniques of implementing image processing in a suppressed circuit scale and improvement of the data processing speed.
In Japanese Patent Laid-Open No. 2006-186917 (to be referred to as literature 1 hereinafter), image data is divided into a plurality of regions, and image processing is performed for each divided region, thereby suppressing the circuit scale. That is, processing is performed for each of a plurality of images generated by dividing an image such that the data amount that is needed to be stored in a line buffer falls within the line buffer capacity, thereby suppressing an increase in the line buffer capacity. Note that when performing filter processing in this divisional processing, extra pixel regions (to be referred to as overlap regions hereinafter) necessary for the filter processing are added to the pixels of the upper, lower, left, and right ends of each divided image.
Japanese Patent Laid-Open No. 2005-250534 (to be referred to as literature 2 hereinafter) discloses a technique of quickly performing processing of a divided image that needs overlap regions in pipeline processing of the divided image. More specifically, three, first to third storage areas are provided. In the pipeline processing, an input image is written in the first storage area. At the same time, stored divided image data and overlap region images are read out from the remaining second and third storage areas, and image processing is performed. This makes it possible to read out the divided image data and the overlap region images without any influence of the writing of the input image.
In the technique disclosed in literature 1, however, when writing divided images in the DRAM, reading out them from the DRAM, and performing filter processing in divisional pipeline processing, the DRAM access data amount increases. More specifically, overlap regions necessary for the filter processing need to be written in the DRAM in each divided image processing, resulting in an increase in the DRAM access data amount and influence on the data processing speed.
In the technique disclosed in literature 2, when a plurality of overlap regions need to be added to, for example, the left and right ends (or upper and lower ends) of a divided image, it may be impossible to perform correct filter processing because of the configuration using three storage areas. In addition, since unnecessary image data other than the overlap regions also need to be held in the storage areas together with the overlap region images, a large storage area capacity is required. Furthermore, the divided images and the overlap region images need to be stored in different storage areas. In general, the horizontal size of an overlap region at the time of horizontal divisional processing is small. For this reason, when a DRAM is used as the storage area, short burst access to the DRAM frequently takes place. When short burst access to the DRAM frequently occurs, the command overhead increases, and the data processing speed thus lowers.